1. Field of the Invention
The present invention method relates to wireless network access and a related computer system, and more particularly, the present invention provides a method of controlling wireless network access through a wired network access interface and a related computer system.
2. Description of the Prior Art
In a modern information-age society, networks allow large amounts of data, information, multimedia and knowledge, in a form of digital electronic signals, to be transferred and exchanged. This promotes greater interpersonal communication, accumulation of experience, knowledge exchange, and technological advancement. Thus, networks have already become a foundation of the modern information-age society. Wired networks already having a broad, almost universal, foundation, wireless networks are now also rapidly being developed. Wired networks are typically more stable, and can ensure safety and privacy of information; wireless networks, on the other hand, break free from the chains of wired transmission, allowing users to access information sources at any time, in any place, in a mobile and portable way. As wired and wireless networks each have their respective peculiarities, it has become a priority of information technologists to allow users to access both types of networks at a lower cost and with more effective resources for a networked device.
Please refer to FIG. 1, which is a functional block diagram of a computer system 10 of the prior art. The computer system 10 is designed with a central processing unit CPU0, a Northbridge chip NB0, a Southbridge chip SB0, memory 12, a graphics accelerator card 16, a display 18, a peripheral device P0, and a storage device M0. In order to access a wired network 22A and a wireless network 22B, the computer 10 can be designed with a wired network card 20A and a wireless network card 20B. The wired network card 20A is compatible with the IEEE802.3 wired network specification. The central processing unit CPU0 is used to control operation of the computer 10; the Northbridge chip NB0 electrically connects the central processing unit CPU0, the memory 12, and the graphics accelerator card 16, and is used to manage a rapid information exchange between the three. The memory 12 is used to store, in a volatile fashion, information and programs needed while the central processing unit CPU0 is operating. The central processing unit CPU0 uses the graphics card 16 to process image data, and to send the image to the display 18, which then displays the image. The Southbridge chip SB0 connects the Northbridge chip to a plurality of buses (such as PCI, IDE, or USB). The peripheral device P0 (such as a sound card), the non-volatile storage device M0 (such as a CDROM drive or a hard disk drive), the wired network card 20A and the wireless network card 20B are on the buses. The Southbridge chip SB0 primarily manages lower-speed information transfer between the central processing unit CPU0 and the devices connected to the buses.
The wired network card 20A could be a network card that conforms to the IEEE802.3 local area network (LAN) specification. The wired network card 20A is designed with a media access circuit MAC1 and a physical layer circuit PHY1. The wireless network card 20B, on the other hand, could be a network card that complies with the IEEE 802.11 wireless local area network (WLAN) specification. The wireless network card 20B is also designed with a media access circuit MAC2 and a physical layer circuit PHY2. Under the open system interconnection (OSI) architecture, the media access circuit MAC1 and the media access circuit MAC2 are used to respectively implement respective media access control layers for the wired and wireless networks. When the computer 10 is used to access network resources, the media access circuits MAC1,2 can use the corresponding physical layer circuits PHY1,2 to acquire digital information, process the information, and send the information to the computer. Information that the computer 10 sends to the network is packaged by the media access circuit MAC1,2. The media access circuit MAC1,2 also arranges a physical location for the packaged information to access the network, and sends the packaged information to the physical layer circuit PHY1,2. Similarly, the media access circuit MAC1,2 unpacks information received by the physical layer circuit PHY1,2 from the network.
The physical layer circuits PHY1,2 of the wired and wireless network cards 20A,B are respectively used for providing wired and wireless physical layer functionality. Information to be sent to the network, after being processed by the media access circuit MAC1,2, is sent to the corresponding physical layer circuit PHY1,2, which converts the information to a signal suitable for transmission, and transmits the signal. The physical layer circuit PHY1,2 can also receive signals from the network and unpack or demodulate the signals to acquire information contained in the signals, then send the information to the corresponding media access circuit MAC1,2. The physical layer circuit PHY1 used for wired network access is connected to other computers on the wired network 22A (such as other terminals or a server) through a network cable 23. The physical layer circuit PHY2 used for wireless network access further comprises a baseband circuit and a radio frequency (RF) circuit. The baseband circuit performs digital processing on information received from the media access circuit MAC2, then the RF circuit wirelessly transmits the information. RF wireless frequency signals received from the wireless network are received by the RF circuit. Then, the baseband circuit converts the demodulated signal to electronic information that is sent to the media access circuit MAC2.
When the computer 10 accesses network resources, all network cards work with a driver program stored in the memory 12. The driver program manages data transfer between the computer 10 and the network. Taking the wired network card 20A as an example, when the computer 10 starts accessing the wired network 22A, the wired network driver 26A in the memory 12 establishes a plurality of ordered descriptors TxA (with individual descriptors indicated as TxA (1) through TxA(n1)) and a corresponding ordered descriptors RxA (with individual descriptors indicated as RxA(1) through RxA(m1)). The driver program 26A then allocates free space in the memory 12, such as a data transmission allocation DTA and a data reception allocation DRA. Each descriptor TxA,RxA is a pointer used to keep track of a corresponding memory allocation address to which it points. When the computer 10 sends a large amount of information to the wired network 22A, the computer 10 uses the wired network driver 26A to store the information to the data transmission allocation DTA and sets a descriptor TxA (such as TxA(1)) to point to the memory space. When the media access circuit MAC1 of the wired network card 20A begins transfer of the information to the wired network 22A, the media access circuit MAC1 uses the descriptor TxA in the memory 12 to find the information stored in the data transmission allocation DTA, and reads the information from the data transmission allocation DTA. Then, the media allocation circuit MAC1 adds a header and a footer (such as a frame check sequence (FCS)) to package the information, then uses the physical layer circuit PHY1 to send the packaged information to the wired network 22A. If a single data transmission allocation DTA is not enough to completely store the information, the information is broken up and stored in a plurality of data transmission allocations DTA, and a plurality of descriptors TxA point to the respective data transmission allocations DTA. For example, if the information is to be stored in three different data transmission allocations DTA, the wired network driver 26A arranges three linked descriptors TxA(1), TxA(2), and TxA(3) to point to the three allocations DTA, and adds “continue” flags to the first two descriptors TxA(1) and TxA(2) to tell the media access circuit MAC1 that after processing this allocation DTA, the next allocation DTA must also be processed. And, a “stop” flag is added to the third descriptor TxA(3) to tell the media access circuit MAC1 not to access further allocations, i.e. those pointed to by TxA(4) and above, after finishing with the current allocation. Through the method described above, the media access circuit MAC1 can correctly access the data transmission allocations DTA, pointed to by the descriptors TxA(1), TxA(2) and TxA(3), to read the information in the memory 12 to be transmitted to the wired network 22A. In practical application, the media access circuit MAC1 has a direct memory access (DMA) engine that allows the media access circuit MAC1 to directly access the information stored in the memory 12, saving resources of the central processing unit CPU0 and increasing information access speeds and efficiency.
Similar to the system described above for managing data transmission, the wired network driver 26A also allocates the descriptors RxA in memory 12 for managing received information. Each descriptor RxA has a pointer pointing to a corresponding data reception allocation DRA. When the wired network card 20A receives information transmitted to the computer 10 through the wired network 22A, the wired network card 20A also works with the wired network driver 26A to store the unpacked information to the allocation DRA, and similarly sets a descriptor RxA (such as RxA(1)) to point to the allocation DRA. In this way, the central processing unit CPU0 can read the information received from the wired network 22A from the allocation DRA that is pointed to by the descriptor RxA(1). Similar to the transmission control system, if the wired network card 20A must store the received information in a plurality of allocations DRA, the wired network card 20A also works with the wired network driver 26A to set a plurality of descriptors RxA to point to the corresponding allocations DRA. Preferably, the descriptor TxA and the descriptor RxA are both set to types corresponding to an architecture of the transmitted or received data. Taking the descriptor TxA as an example, as information to be sent to the wired network 22A is sequentially stored to different allocations DTA, the wired network driver 26A accordingly sets each descriptor TxA(1), TxA(2), and so on, to point to different allocations DTA. The wired network card 20A also accesses each allocation DTA pointed to by a pointer according to the sequence of the descriptors TxA(1), TxA(2), and so on. This happens until the last descriptor TxA(n1) is reached, at which point, the wired network driver 26A loops back to the first descriptor TxA(1), and continues to set the descriptors TxA(1), TxA(2) in sequence to point to following allocations DTA of the stored transmitted information. The media access circuit MAC1 of the wired network 22A also accesses each allocation DTA pointed to by the descriptors TxA according to the looped sequence. The descriptors RxA are also used in the looped style described above.
As with the principles described above for access of the wired network 22A, the prior art computer 10 also uses a wireless network driver 26B with the wireless network card 20B to allocate a plurality of descriptors TxB (indicated individually as TxB(1) through TxB(n2)) and a plurality of descriptors RxB (indicated individually as RxB(1) through RxB(m2)) for pointing to a data transmission allocation DTB and a data reception allocation DRB. Information to be sent to the wireless network 22B is stored in the memory allocation DTB pointed to by the descriptors TxB, and information received from the wireless network 22B is stored in the memory allocation DRB pointed to by the descriptors RxB. For the computer 10 to access the wireless network, the media access circuit MAC2 and the central processing unit CPU0 use the descriptors TxB and RxB to access the information sent to the wireless network, and received from the wireless network, stored in the memory 12.
Although the wired network card 20A and the wireless network card 20B both use descriptors to manage network-accessible information, the descriptors used to access the wired network (TxA and RxA) and the descriptors used to access the wireless network (TxB and RxB) have different information structures. To accommodate special demands of the wireless network, the descriptors TxB and RxB used for accessing the wireless network must further indicate a particular status of the wireless network. For example, because the wireless network 22B and the computer 10 are not connected by a physical network cable, when the computer 10 transmits a large amount of wireless information to the wireless network 22B, the computer 10 has no way of confirming that the information sent wirelessly by the wireless, network card 20B has already been received smoothly by another computer on the wireless network 22B. At this time, the central processing unit CPU0 requests that the wireless network 22B send to the computer 10 an acknowledgement of data having been received completely. In practice, when the central processing unit CPU0 uses the wireless network driver 26B to store the information to the memory allocation DTB, the central processing unit CPU0 arranges the descriptor TxB to point to the memory allocation DTB, and the descriptor TxB indicates the acknowledgement required by the wireless network 22B. When the media access circuit MAC2 of the wireless network card 20B accesses the information according to the descriptor TxB, the media access circuit MAC2 uses the descriptor TxB to know to request acknowledgement from the wireless network 22B. In this way, when the media access circuit MAC2 packages the information, the media access circuit MAC2 adds acknowledgement information to the head of the packet. The packet is then sent to the physical layer PHY2, and the physical layer PHY2 sends the packet wirelessly to the wireless network 22B.
Practically speaking, in an architecture such as IEEE 802.11, aside from the acknowledgement request, there are a number of settings that are different from those of the wired network. For example, as information is transmitted wirelessly, in addition to the transmitter and the receiver, any third party that can receive wireless signals could intercept the wirelessly transmitted information. In order to ensure that the information content does not leak, the IEEE 802.11 architecture provides a wired-equivalent privacy (WEP) mode, which encrypts transmitted and received information at both ends, and maintains basic information security. The central processing unit CPU0 also uses the descriptors TxB and RxB to govern whether or not the media access circuit MAC2 uses WEP to access network resources. Also, in order to adapt to a portable nature of computers employing the wireless network architecture, in the wireless network architecture, each computer connects to the network at an access point. More specifically, when the computer 10 accesses information on the wireless network 22B, the computer 10 establishes contact to get a basic service set (BSS) organized by an access point. The basic service set can comprise a plurality of computers, all connected wirelessly to the BSS through connection to the access point. A physical wireless network address of the access station could act as a basic service set identification (BSSID). When a first computer in a first basic service set connects to a second computer of a second BSS, the first computer first contacts an access point of the first BSS. The access point of the first BSS connects to an access point of the second BSS through a distribution system service (DSS), then connects to the second computer through the second access point, allowing the first computer to contact the second computer. In the wireless connection process just described, each computer must make contact with a respective access point, enter/exit the BSS, access the DSS through the access point, etc. And all of these matters occur between the computers and the access points with the help of management and control framework information, such as BSSID's, acknowledgements, and beacons. In the prior art architecture of FIG. 1, many internal control and management signals must be produced between hardware internal to the computer 10, and are made known to the central processing unit CPU0 and the media access circuit MAC2 through the descriptors TxB and RxB. In contrast, in wired network access, because data transfer has a safe path through network cables, the access control system can be relatively simple, and the descriptors used by the wired network need not be as complicated as their wireless counterparts. Thus, the two types of descriptors used in the prior art are certainly not similar, and cannot share software and hardware resources.
Due to the above-mentioned differences in accessing the wired network 22A and the wireless network 22B, the descriptors TxB and RxB used for wireless network access and the descriptors TxA and RxA used for wired network access are neither similar nor compatible. And, when the prior art computer 10 needs to simultaneously access both wired and wireless network resources, the wired network driver 26A and the wireless network driver 26B must individually allocate descriptors used by both the wired network and the wireless network. In a modern, highly networked information society, networking power has already become a fundamental computer requirement. Effectively integrating wired and wireless network access capabilities, and simplifying wireless and wired network access control systems has also become a goal of information industry research and development. However, in the prior art, integration of wired and wireless network access is not possible because the forms of the respective descriptors are different. Similarly, as the descriptors allocated by the wired and wireless network drivers are not compatible, the media access circuits MAC1 and MAC2, which must get information related to network access from the descriptors, are difficult to integrate as simplified circuits.